This invention relates to an electrically programmable read only memory device (EPROM) and more particularly to an improved integrated circuit semiconductor EPROM comprised of an array of closely packed memory cells each utilizing a single transistor element. It also relates to a method for making such an improved device.
In the field of semiconductor memory devices electrically programmable read only memory devices (EPROM's) have been suggested which utilize electron injection using a so-called floating gate in combination with the gate of a metal oxide silicon field effect transistor (MOSFET). The memory cell was programmed by charge transport to the floating gate by injection of electrons from source-substrate or drain-substrate junctions or the conducting channel. Earlier devices previously designed utilized a planar type layout on the semiconductor chip wherein the floating gate region was located parallel to the device regions in the conventional manner. This arrangement required a substantial amount of chip area for each EPROM cell and hence a relatively large area for the entire device since such EPROM devices normally utilize a large number of cells. The excessive area problem of planar devices was greatly alleviated by the development of the VMOS type reprogrammable semiconductor memory device as described in co-pending application for U.S. Letters Patent, Ser. No. 683,185, filed May 4, 1976 and assigned to the assignee of this application. The V-MOS type EPROM, as previously disclosed, comprised an array of single V-type MOSFET memory cells formed at the crossover locations of word address lines and bit lines. Each MOSFET comprised a V-shaped recess that extended through a bit line of N-type conductivity material, through an epitaxial P layer and into a substrate of N type material providing a grounded source for the device.
Although the aforesaid V-MOS type EPROM provided a major advantage by reducing the area required per cell, it only partially solved a further and equally important problem with planar type EPROM devices, namely that of reducing the voltage required to accomplish programming of the device. With planar type devices the programmable voltage required was relatively high and often within 10% of the maximum device voltage allowable. Thus, an inadvertent application of only a relatively small excess voltage during programming could destroy the device. Attempts to lower the programming voltage are blocked by the fact that variations in doping levels and sizes of the device topology elements which were necessary to cause a reduction in programming voltage also inherently caused an increase in device threshold voltage, thereby making it either too slow or altogether inoperative. The V-MOS EPROM provided a partial solution to this problem by its mere geometry. However, it is one object of the present invention to provide an even more effective and efficient V-MOS EPROM device that allows a substantial reduction in required programming voltage and yet has a relatively low threshold voltage compared with prior EPROM devices.